Pipelined Architecture

The Z8 core has a pipelined architecture which means fetch and instruction cycles overlap.



The first instruction gets fetched and executed. LDX here for example takes 3 cycles to fetch and 4 to execute. The first instruction takes 7 cycles because there were no bytes pre-fetched. When another LDX comes after that it already fetched the instruction while the other LDX was still executing. Fetch and instruction cycles overlap. The fetch unit cannot fetch a new instruction while the last instruction is still loading though. Only while the previous instruction has loaded the next one can be loaded in the cpu. Same with the instruction cycles. The next instruction cannot execute unless the previous one finished executing.


When a branch occurs (a jp instruction for example) the pipeline is flushed. Flushing the pipeline takes an addition clock cycle. After a jump occured there are no instructions pre-fetched. Keep this in mind when counting clockcycles.

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