I/O ports are mapped to registers. These registers are special purpose. In order to address them you have to use extended addressing (12 bit vs normal 8 bit).
Example: LD dest,src [becomes] LDX dest,src
|Table 1. GPIO Port Registers and Subregisters|
|Port register mnemonic||Port register description|
|PxADDR||Port A-H Address Register (r/w selects subregisters)|
|PxCTL||Port A-H Control Register (r/w to/from selected subregister)|
|PxIN||Port A-H Input Data Register (read-only)|
|PxOUT||Port A-H Output Data Register (r/w)|
|Subregister mnemonic||Port register description|
|03h||PxOC||Output Control (Open-Drain)|
|05h||PxSMRE||Stop Mode Recovery Source Enable|
Selecting a subregister and writing to it:
ldx PBADDR, #01h ;Select subregister Data Direction ldx PBCTL, #03h ;Pin B0 and B1 are now inputs. The rest are outputs. 0=output, 1=input
Write to the output register:
ldx PBOUT, #04h ;Pin B2 is now HIGH. The other output pins are LOW
Read from input register
ldx R0,PBIN ;Load the content of the input register into working register R0.
Notice that you have to use extended addressing to be able to access these registers. They are not in range of standard 8 bit addressing.
You can use regular LD instructions to write to ports and effectively halve the time it takes to set up the registers. This optimization is only beneficial when you need to write to more than one register. It is both memory and cycle efficient.
In order to use the normal addressing mode you have to set up the Register Pointer using the SRP instruction. Make it point to the start of the block of 16 registers of the peripheral you want to control.
;This is optimized srp 0FDh ; Set register pointer to address 0FDh (2 execution cycles, 2 fetch, 2 bytes of memory) ld R8,#10h ; Set register 0FD8h to 10h (2 execution cycles, 2 fetch, 2 bytes of memory) ld R9,#EFh ; Set register 0FD9h to EFh (2 execution cycles, 2 fetch, 2 bytes of memory)
;This is NOT optimized ldx 0FD8h,#10h ; 2 execution cycles, 4 fetch and 4 bytes of memory ldx 0FD9h,#EFh ; 2 execution cycles, 4 fetch and 4 bytes of memory
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