(Serial Peripheral Interface)
Initialize spi:
ldx PCADDR,#DDR ;Set MOSI and SCK to output, MISO to input, SCK to output ldx PCCTL,#1110_0111b ldx PCADDR,#AF ;Set alternate SPI functions ldx PCCTL,#0011_1100b ;MOSI,MISO,SCK,/SS ldx SPICTL,#000__11__011b ;SPI mode Master, transmit on falling edge, SCK idle HIGH ldx SPIMODE,#00_0_000_1_1b ;8 bits per char, SS is output and set to 1 ldx SPIBRH,#0 ;spi_frequency = clock_frequency / (SPIBR[15..0]*2) ldx SPIBRL,#2 ;the highest spi rate: SPIBRH = 0000h → clock/2
Some handy macro's:
spi_start: macro andx SPIMODE,#~1 endmac spi_stop: macro orx SPIMODE,#1 endmac spi_stop wait_spi_rdy: macro $$: ldx R0,SPISTAT btjnz 1,R0,$B endmac wait_spi_rdy
To transmit:
;.... sending bytes spi_start ld R1,#5 call spi_transmit ld R1,#10 call spi_transmit ;.... first 5 is sent, then 10 is sent spi_transmit: wait_spi_rdy ldx SPIDATA,R1 wait_spi_rdy ret
Please submit corrections, suggestions, and new documentation here: Submit a ticket
← Return to Reference Index
This is not an official Zilog website. Zilog nor 8times8 are liable for any damage done to equipment. Tutorial and reference copyright ©8times8 Creative Commons CC-0 License (public domain.) This reference uses content from Zilog's technical datasheets. Fair use only. Datasheets copyright © 2013 Zilog®, Inc. Z8, Z8 Encore!, Z8 Encore! XP and Z8 Encore! MC are trademarks or registered trademarks of Zilog, Inc. Read Zilog's terms at zilog.com
Website design by Koen van Vliet. Hosted by sourceforge.net